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application note a new generation of very low drop voltage regulators by riccardo erckert 1. a little bit of history the first available regulators still had external power transistors. at that time this was the most economic solution to satisfy both technical and economical requirements of the customer. quite soon the power transistor was integrated. it was implemented as a npn transistor (mostly in dar- lington configuration) because integrated npn transistors can handle significantly higher current densities than lateral pnp transistors. the draw- back of this configuration was the required volt- age drop between input and output of the regula- tor in the range of 2v leading to higher power dissipation according to the minimum required drop. the next step was the low drop regulator using an darlington output transistor consisting of a pnp driver and a npn power transistor. this structure reduced the voltage drop required downto about 1.1v. then the very low drop regu- lators using pnp transistors as power transistors became more and more popular. the reason were requirements driven by application such as proper function even at very low input voltages (for example in automotive applications while the starter is working). 2. characteristics of a standard regulator topology fig. 1 shows the block diagram of a standard volt- age regulator in application. AN682/1194 figure 1: standard voltage regulator using a darlington output monolithic voltage regulators have become a standard device of modern electronics. most of to- day's pc-board designers tend to use them just like transistors or resistors. in reality these versatile devices have a quite complex internal structure. so some basic rules should be respected for their application. 1/16
the operational amplifier can be described as a voltage controlled voltage source and a low pass filter. the control voltage is nothing else than the difference between the reference voltage and the divided output voltage. the output stage consists of a darlington emitter follower which can roughly be modelled as a follower stage with a voltage gain of one and an output impedance of two times vt divided by the output current plus the current sense resistor. fig 2 shows this repre- sentation. let us see the behaviour of this kind of regulator. the dc performance is defined by the output im- pedance r2 (r2 is the current sensing resistor use for the short circuit protection) in series with the emitter impedance of the output transistor re (supposing the load resistance is much higher than r2 and re it is neglected) and the dc gain k of the operational amplifier (usually several hundred to some thousand). vout = vref + v12 ? k - (r2+re) ? iout (2.1) in this equation the deviation of the output voltage v12 can be derived. this yields dv12 diout = ( r2 + re ) k (2.2) equation (2.2) describes the dc output resistance of the voltage regulator. the frequency response of the operational amplifier is modelled by r1 and c1. approaching the gain bandwidth product of the operational amplifier k becomes one and the output impedance of the whole regulator is mainly determined by r2 and re. the value normally is in the range of one ohm or even less. so the cut- off frequency of the output impedance and the ex- ternal capacitor c2 becomes fg2 = 1 2 p ( r2 + re ) c2 (2.3) assuming c2 around 100 nf, fg2 is in the range of several hundred kilohertz. so r1 and c1 are designed to become the first pole reducing the loop gain to less than one at fg2. fg1 = fg2 / k (2.4) fig 3 shows the typical open loop gain and phase curves of the regulator. the gain becomes less than one before the sec- ond pole shifts the phase an other 90 degrees. when the total phase becomes (including phase inversion of the regulator itself) 360 degree the gain must be less than 0 decibel (corresponding a loop gain of one) to provide stability. this kind of regulator is quite economical and ro- bust. the drawback is the voltage drop between input and output of the device. to keep up regula- tor function two vbe plus a certain headroom for the operational amplifier is required. this adds up to about two volt at low temperature! figure 2: representation of the topology of fig. 2 by voltage controled voltage sources figure 3. application note 2/16
3. the very low drop regulator to overcome the voltage drop restriction of the standard topology very low drop regulators have been introduced. the very low drop regulator uses a pnp transistor in it's power stage. so the drop required for proper function falls downto the saturation voltage of this pnp transistor, which is in the range of some hundred millivolts. fig 4 shows the topology of such a very low drop regu- lator including it's load and external capacitors. here the output is driven by a collector. so the stage consisting of q1 and q3 can be repre- sented by a voltage controlled current source. the output current is transformed into an output voltage by integrating this current with c2. the control voltage is the base voltage of q1. nor- mally q1 is a darlington transistor in this kind of circuit. as it is easier to implement in integrated circuits, the amplifier op usually is built as an an operational transconductance amplifier. this yields the idealized circuit shown in fig. 5. i1 is the operational transconductance amplifier mentioned above. as the voltage divider of the feedback loop is omitted the reference voltage vref now becomes the equal to the desired output voltage. (the voltage divider found in most regu- lators just introduces a constant factor into the loop.) i2 represents the output stage consisting of q1..q3. r6 represents the input resistance of the second stage. so the integrated circuit converts a deviation between the output voltage and the ref- erence voltage into an output current. to make an output voltage of this current the integrating behaviour of c2 is mandatory. this automatically makes the external capacitor together with the figure 4: very low drop regulator figure 5: representation of a very low drop regulator by voltage controled current sources application note 3/16
load impedance r5 define the first pole! this is a completely different situation compared to the standard voltage regulator described in paragraph two. of course c2 being an electrolytic capacitor is far from making it an ideal integrator. the effec- tive series resistance esr already becomes dominant at considerably low frequencies around some hundred herz. the first cut-off frequency where the integrating behaviour of the loop be- gins, can be calculated by: fg1 = 1 / 2 p r5 c2 (3.1) at fg2 the effective series resistance becomes dominant devaluating the integrator again. equa- tion (3.2) yields this frequency. fg2 = 1 / 2 p c2 esr (3.2) at fg2 the loop gain is still much higher than one. to maintain stability, a well defined second low pass must reduce the gain downto one before fur- ther phase shifters add an other 90 degrees caus- ing instability. (example: supposing your appli- cation can tolerate an output voltage change of 20 mv at a load change of 400 ma the required transconductance of the complete regulator can be calculated. s12 = 400 ma / 20 mv = 20 a/v with an esr of one ohm this yields a loop gain of gain = s12 ? esr = 20 (or 26 in decibel.) a good choice is making fg2 the cut-off frequency of the chip internal fre- quency compensation. so c1 becomes c1 = 1 / 2 p r6 fg2 (3.3) with r6 = b ? r2 (3.4) where r2 is the emitter resistor of figure 4 and b the gain of the driver transistor q1. to keep c1 in a feasible range, q1 usually has to be a dar- lington transistor. at a certain frequency, let us call it fg3, further parasitic poles become a matter of concern. there the phase shift of the low pass c1 should decrease. (this frequency is deter- mined by chip internal propagation delays. these delays may be quite significant in low consump- tion devices requiring extremely high internal im- pedances while pocket capacities even increase due to large resistors. reducing the pocket ca- pacities associated with the pocket size isn't pos- sible because the device might have to handle a wide supply voltage range.) this yields the value for resistor r1. r1 = 1 / 2 ? p ? c1 ? fg3 (3.5) if fg3 is determined by multiple parasitic poles the loop gain must under all circumstances be less than one at this frequency. then a maximum value for the tolerable esr is given by: esrmax = fg3 / s12max ? fg2 (3.6) with fg2 according to the internal compensation described by equations (3.3) and (3.4). if fg3 is only determined by a single parasitic pole the situation becomes a little more relaxed. fig 6 shows a bode plot of the cut open loop of such a very low drop regulator with multiple parasitic poles representing the worst case in an applica- tion, where the external pole is exactly fitted with the internal (on chip) frequency compensation. fig. 6 shows the ideal case of solving equation (3.2) and (3.3) giving the same frequency fg2. this is not always the case. depending on the practical value of the effective series resistance equation (3.2) and equation (3.3) may give different frequen- cies for fg2. supposing an esr less than esrmax we obtain a bode plot similar to fig. 7. figure 6. application note 4/16
here the phase margin approaches zero degrees between fg2a and fg2b. fortunately the two inte- grators involved (external capacitor c2 and inter- nal capacitor c1) are degraded by the series re- sistors r1 and the esr. so analytic calculation omitting approximations show that the loop will stay stable. nevertheless the regulator will tend to ring if the effective series resistance esr be- comes too small. as the charge and discharge currents of c2 are limited the ringing signal may become triangular shaped in many applications. 3.1 reaction on load transients we have seen the bode plots of standard regula- tor topologies and very low drop topologies differ a lot. let us now investigate the reaction on load changes. an abrupt increase of the load current will have to be satisfied by the output capacitor (c2 in fig. 5) first because the collector of the power pnp transistor will in the beginning act as a current source providing just the same current as before the load change. due to the esr of this capacitor the output voltage will drop immediately. equation (3.1.1) calculates this impact. d vout = esr d iout (3.1.1) then the capacitor will be discharged until the regulator reacts. the initial slope is defined by: dvout dt = d iout c2 (3.1.2) abrupt reduction of the load current will have a similar effect. first the output voltage increases immediately according to equation (3.1.1) again. then c2 will be charged. equation (3.1.2) de- scribes this if d iout is inserted with a negative sign. after this overshot the regulator will turn off and the capacitor c2 will be discharged again by the reduced load current. again equation (3.1.2) can be used. keep in mind very low load currents after an abrupt change will lead to a long time constant of the overshot! fig. 8 illustrates this be- haviour. figure 7. figure 8. d d application note 5/16
3.2. reaction to supply voltage transients the reaction to supply voltage transients is de- pending much on details of the circuit of the regu- lator. in general low consumption devices tend to be more sensitive because high internal imped- ances together with the technology dependant (and so they are supply voltage dependant!) pocket capacities need more time to recover from transients. nevertheless some optimisation can be achieved by smart design. designs using integrated prestabilisation circuits to supply the high performance reference and regulator blocks may lead to almost transient im- mune circuits! the standard l4938 family already uses a simple prestabilization guaranteeing good transient performance at a supply voltage range from 7v to 40v. the prestabilisation is straight forward using a low precision bandgap that is only optimised for transient robustness. the precision reference is generated in a second bandgap that is optimised for high accuracy. although this is an easy to understand design this prestabiliser has certain limitations: supplying everything from the input the device still is prone to negative supply transients (below 7v). the independant prestabilising bandgap con- sumes an additional supply current of about 40 m a which could not be tolerated for extreme low con- sumption applications. the l4938e family uses a new approach to solve the disadvantages of the independant bandgap prestabilisers. some vbe are added to the refer- ence voltage. this is used as the bias of the prestabiliser. additionally the prestabiliser has a second supply path from the output out1. in fact as soon as the output voltage (at out1) is high enough all the internal circuitry of l4938e is sup- plied by out1. the supply path from vs is only required to start the device. so transients on vs will not harm the performance as long as the sup- ply pin doesn't go below 2v (which is required by the starter). of course during the time the input voltage is less than the desired output voltage the load has to be supplied by the output capacitor. 4. the l4938e family in detail as we have been entering into circuit specific characteristics let us see the schematic of the l4938e family . the two voltage regulators reg1 and reg2 are of figure 9 application note 6/16
the very low drop kind discussed before. regula- tor1 is permanently active. regulator2 can be en- abled by a logic low at input en. if reg.2 is dis- abled the total current consumption of the l4938e is 70 m a (typically) plus the base current of q21, which is 1/40 th of the load current. 4.1. regulator 1 regulator 1 is capable of supplying loads up to 100ma. the effective series resistance of the ex- ternal capacitor (see fig 5) c2 should be less than 5 w . the capacity should be more than 10 m f. in most applications external capacitors (c2 in fig. 4) around 22 m f are to be expected. the load (r5 in fig. 4) will range from several k w down to 50 w . supposing a load of 500 w and an effective series resistance of one ohm the first (almost) in- tegration will start at: fg1= 1/2 p ? 22 m f ? 500 w = 14.5 hz (see eq. 3.1) and end at: fg2b = 1/2 p ? 22 m f ? 1 w = 7.2khz (see eq. 3.2) in reg.1 the base impedance of q11 (which actu- ally is a darlington transistor) represented by r6 of fig 5 is approximately 3.5 m w . consequently the second integrator with a capacity of 33 pf will take over at fg2a = 1.4 khz this is the optimised value for a worst case esr of 5 w . so we find two almost integrating low pass filters between 1.4 khz and 7.2 khz. fortunately they both are damped and shift phase by slightly less than 90 deg. each thus keeping the loop sta- ble. nevertheless using extremely low esr val- ues the loop will (as all very low drop regulators do) tend to ring after transients. with esr values of more than some tenth of an ohm ringing will al- ready disapear (esr values approaching zero correspond to a low fg2a in figure 7). in this fre- quency range some phase margin has to be sac- rificed in favour of leaving margin for higher esr values. beyond 70 khz parasitic capacities inside the regulating amplifier begin to act as a further single order pole. therefore r1 devaluates the in- tegrator c1 at: fg3 = 1/2 p ? 33pf ? 70k w = 69khz keeping the phase margin until further poles make the amplifier more and more behave like a delay line above 200 khz. fig 10 shows the re- sponse of the regulator to load changes. figure 10: response of the regulator to load changes. top trace: middle trace bottom trace drive of load transistor. high correspond 100 w . low corresponds no load. response with 10 m f, esr = 4.7 w ; 0.5v/division. response with 10 m f, esr approaching 0; 0.5v/division application note 7/16
figure 11: temperature dependence of the output voltage of out1 figure 12: response to the load changes. top trace: middle trace: bottom trace: drive of load transistor. high correspond 100 w load. low corresponds no load. response with 10 m f, esr approaching zero (plastic capacitor); 0.5v/division. response with 10 m f, esr = 4.7 w ; 0.5v/division application note 8/16
the regulator is committed to high precision using state of the art circuitry cancelling base currents by dummy transistors and cancelling leakages by symmetrizing the circuit with dummy leakage gen- erators. fig 11 shows the result of these efforts. the regulator is of course protected against over- load and against over temperature. thermal shut down of regulator 1 takes place at a 10 k higher temperature than thermal shut down of regulator 2. so in critical application the output of regulator 2 can be monitored as a prealarm before regula- tor 1 shuts down too. the thermal shut down is an analogue one regulating down the output volt- age until power dissipation inside the chip and the thermal conduction balance. 4.2 regulator 2 regulator 2 is designed very similar to regulator 1. besides the features of regulator 1 regulator 2 can be disabled by a logic high at pin en. this reduces current consumption significantly. (stand by consumption specified in the data sheet is ref- ered to regulator 2 being disabled.) as this regu- lator has to provide more current than regulator 1 all internal impedances and current densities are scaled according to the higher maximum output current. so all parasitic cut-off frequencies shifted higher and frequency compensation had to be de- signed different. cut-off frequency fg3 has been found at fg3 = 190 khz this allows choosing the cut-off frequency fg2 at 7 khz. so regulator 2 will recover faster from load transients. fig 12 shows the response to load changes. like regulator 1 regulator 2 is optimised for maxi- mum accuracy. regulator 2 has a thermal shut down. this shut down takes place before regula- tor 1 turns off. 4.3 the reset circuit the reset circuit consists of three major parts. comp 1 supervises the output voltage of out1. the external capacitor, that may be connected to pin ct together with comp 2 provides a well de- fined minimum reset pulse width. the or gate between comp 2 and q6 supervises the bandgap voltage forcing res low as soon as the refer- ence breaks down corrupting the operation of comp 1. 4.3.1 the reset path via the comparators comp 1 compares the divided output voltage with the reference inside the circuit. pin pr left open the reset threshold is typically 300 mv below the nominal output voltage. to alter the reset thresh- old pin pr can be connected to ground via a re- sistor or even be shorted to ground. by this meas- ure the reset threshold can be programmed between typically 3.8v and 4.7v . the resulting threshold can be calculated by v res = 4.7v ? ( r pr + r6 ) r pr + r5 + r6 (4.3.1) with r pr being the external resistor r5 = 20k w and r6 = 80k w , r5 and r6 are matched but have an absolute tolerance of 20%. if vout1 falls below the reset threshold, q5 dis- charges the capacitor at pin ct. the pull down current ict is between 3 ma (at -40 deg. c) and 15 ma (at 150 deg. c). consequently the reset is delayed depending on the capacitor at ct. trr = 3v ? ct / ict + t rr0 (4.3.2) t rr0 is the propagation delay of the reset circuit without capacitor. t rr0 is around 15 m s as soon as vct drops below vbe the logic output res becomes low. it will remain low until the voltage at ct reaches 1.4v again. the minimum reset time is t rdmin = (1.4v - vbe) ? ct / 1 m a (4.3.3) depending on the junction temperature vbe ranges from 0.2v to 0.7v this minimum time reset will only take place after extremely short impacts on the output that does not allow full discharge of ct. normally ct will be discharged downto the saturation voltage of q5. the nominal reset delay then becomes t rdnom = (1.4v - vsat) ? ct / 1 m a (4.3.4) vsat is always around some millivolts. t rd always starts at the time the output has recov- ered again. fig 13 shows a typical timing of the reset circuit. application note 9/16
4.3.2 the default reset path of course functionality of this reset circuit requires a correct bandgap voltage reference. but the bandgap reference being an enhanced precision circuit incorporates cascode amplifier stages avoiding early effects. therefore depending on temperature it requires a certain supply voltage (min v bg +3 ? v be +2 ? v sat = 3.5v at ambient temperature). without controlling the bandgap voltage, a race between the supervised output voltage and the reference voltage could occur if the bandgap supply (that is taken from vs or out1 whatever is available) falls below a certain level. consequently the input of the or gate be- tween comp 2 and q6 checks the bandgap circuit for a correct reference value. if the bandgap volt- age is found to be too low a low at output res is initiated without caring for any conditions met at pin ct. the or gate driving q6 is supplied from out 1. so the low at res can be held until out1 drops below v be . this feature is a must in modern microprocessor systems. imagine what would happen if your microprocessor changes the system eeprom during the last maybe three volts of the falling slope of the supply voltage just because the reset has become high again which could happen with some older reset circuits. the whole reset circuit is always active. it is not turned off in stand by mode (en high). 4.4 comparator comp 4 comp 4 is an uncommitted comparator for exam- ple to be used to generate an alarm before reset occurs when the supply vs is turned off. the bandgap voltage is used as its reference. due to the drive current of q7 the comparator cunsumes more current if input si is low (v si 1.23v). like the reset circuit the comparator is permanently active, but it has no default path activated by bandgap fails. 5 emi considerations although it is a low current consumption device the l4938e is optimised for rough automotive en- vironment. special care was taken to make it in- sensitive to supply transients and input transients at en and si. figure 13. application note 10/16
5.1 protection of the internal reference voltage generator the bandgap being the heart of the l4938e is supplied by an internally prestabilized rail. fig 14 shows the simplified prestabilization. transients at vs will only have little influence on the bandgap voltage. this can be measured at pin pr if it is left open. fig 15 shows the pulse re- sponse of the bandgap together with the prestabi- lization. figure 14: simplified presabilization figure 15: supply transient response of the bandgap reference circuit. top trace: bottom trace: supply voltage; 5v/division response transient response; 200mv/division. (measured at pin pr) application note 11/16
5.2 voltage regulators like the bandgap the regulating amplifiers are supplied by an internal rail. so their response to supply transients is quite moderate as can be seen on fig. 16 . injecting rf into sensitive feed back loops can lead to malfunction of the regulators if certain val- ues are exceeded. actually the outputs out1 and out2 and feedback input adj should be kept free from rf. between out2 and adj there should be no low pass because this would shift the phase of the regulation loop. this reduces stability of the loop or could even cause oscilla- tion. the best solution is blocking the outputs with an smd ceramic capacitor connected to ground as near to the circuit as possible. 5.3 reset circuit to make reset insensitive it is supplied by the in- ternally presabilized rail too (except the drive of q6). to make the default path insensible too an on chip delay of approximately 20 m s is imple- mented. even without the use of an external de- lay capacitor at pin ct reset has become very ro- bust. this can be seen on fig. 16 too. the pins ct and res being open collectors incorporate a lateral npn transistor that will be activated if one of those pin is dragged below -v be . if this un- avoidable parasitic is activated it can cause unex- pected results in other parts of the circuit. to keep antennas inefficient the capacitor at ct should be connected with short wires. as leak- ages in smd ceramic capacitors were reported we recommend the use of a foil capacitor. output res is suited to drive logic devices on the same board as the l4938e . long wires or wires leav- ing the board may therefore require rf blocking means. pin pr is directly connected to the bandgap that is the heart of the circuit. so this pin should either be connected to a resistor to ground using the shortest possible way (small an- tenna loop) or left open. dangling wires con- nected to pr could act as an antenna and there- fore are to be avoided. 5.4 sense comparator and enable input in automotive applications ground bounce of sev- eral volts is quite common. so the inputs en and si are hardened against negative input pulse downto -20v by a special protection structure. be- sides the protection this structure acts as a low pass too. fig 17 shows the simplified schematic of this protection and the resulting input charac- teristic. figure 16: supply transient response of the voltage regulators and reset circuit. top trace: second trace: third trace: bottom trace: supply voltage; 20v/division reset output connected to out1 via 10k w (no reset fail). out1; 0.2v/div. load = 100 w out2; 0.5v/div. load = 33 w application note 12/16
the comparators comp 3 and comp 4 have reac- tion times of several microseconds to make the insensible to short transients. like res the sense output so is an open collector topology and should not be reverse polarised. 5.5 reverse supply protection. the supply voltage may be reverse polarised to - 14v without destroying the device. of course it doesn't work anymore then. even during reverse supply condition the outputs out1 and out2 re- main at a minimum voltage of -v be because the power transistors are turned off then. compo- nents supplied by the l4938e under normal cir- cumstances will not be harmed. 6. special application considerations having become aware that very low drop voltage regulators require some care about effective se- ries resistances of the output capacitors and about harsh load transients there should not be many problems left in standard applications. nevertheless let us have a look at some maybe less typical circuits. 6.1 using out2 as a high side switch sometimes only one 5v supply and a high side switch is needed in an electronic system. this typically is the case if a microprocessor is working together with interface circuits that may be oper- ated throughout the whole voltage range of the system supply (vs of the l4938e). here it be- comes a very attractive solution to use out2 of the l4938e as a high side switch turning on the supply of the interface circuits as soon as the sys- tem changes from stand by to operation. so the system will work with a low stand by consumption even if the interface circuits require a certain sup- ply current (because the supply of the interface circuits will be turned off in stand by mode). for such applications pin adj only has to be discon- nected from out2 (leaving pin adj open or shorting it to ground will yield the same behav- iour). now regulator 2 will be driven into dropout operation as soon as it is enabled (en=low). with an opened regulation loop the output capaci- tor of out2 is not required for stability anymore. nevertheless we recommend a certain capacity to avoid undershots of out2. two conditions how- ever should be considered carefully. supply voltage range: as the loop is cut open out2 will just follow the supply vs. the esd protections of out2 are suited for a maxi- mum output voltage of 20v. therefore opera- tion with supply voltages higher than 20v us- ing the regulator as a high side switch may be destructive for the protections of out2 (be- cause the esd protection at out2 could ignit and keep conducting at a high current for a longer time than it is suited for.). inductive loads: inductive loads such as long wires or inductors may cause an undershot of out2 at turn off. undershots below -vbe at out2 activate parasitic components and must be avoided under all circumstances. ap- propriate means to avoid such undershots are clamps using shottky diodes or an output ca- pacitor fulfilling equation (6.1.1) . c out2 >l ? i 2 /v 2 out2 (6.1.1) c cout2 is the capacity attached to out2 l is the inductivity of the load i is maximum current flowing before turning off the switch v out2 is the minimum voltage c out2 is charged to before the switch turns off. 6.2. paralleling of outputs if both outputs are paralleled the different regula- tion loops may interfere with each other. this may lead to instability although each regulator indi- vidually is stable. (some single poles of the two regulators are realtively close. depending on load conditions paralleling the regulators may lead to figure 17: en, si negative transient protection. application note 13/16
pole splitting converting two poles on the real axis into a complex pair of poles.) paralleling of out- puts should not be done for this reason. if this can not be avoided due to specific conditions of an application the outputs at least should be decou- pled by a resistance of some ohm or by a diode. stability in such applications should be investi- gated by the user very carefully. 6.2.1 long common ground wires for both output capacitors connecting the ground node of the output capaci- tors to ground far away from the regulator can lead to the same situation as paralleling the outputs be- cause there will be an ac short circuit between out1 and out2. this is illustrated by fig. 18. here c1 together with esr1 represents the out- put capacitor of regulator1 while c2 together with esr2 represents the output capacitor of regula- tor2. r1 is the resistance and l1 the inductivity of the ground wire between the common ground node of c1 and c2 and the ground node of the voltage regulator. if the effective series resis- tances esr1 and esr2 become small compared to r1 and the ac impedance of l1 the output ca- pacitors act as ac short circuits between the out- puts. so the output capacitors should be con- nected to the ground pin of the regulator the shorts possible way. if this can not be accom- plished separate ground wires for both capacitors should be used (star ground configuration). 6.3 triggering reset on out2 ramp down to supply large microcomputer systems the cur- rent capability of out1 may not be sufficient. so it may be helpful to use out2 to supply the mi- crocomputer. now reset supervises the wrong output. this situation can be overcome by using the sense comparator to control out2. the out- put of the comparator is used to discharge the timing capacitor ct. this circuit can be seen on fig.19. in this circuit reset will take place if out1 drops below 4.7v (pin pr is left open) or if out2 drops below 4.5v. changing the values of r1 and r2 other reset thresholds can be programmed. r3 is just the pull up for the open collector output res. depending on the specific application r3 may be connected to out2 just as well. figure 18: equivalent circuit of long common ground wires figure 19: triggering reset on out2 ramp down application note 14/16
6.4 using the bandgap reference of l4938e for auxiliary circuits l4938e offers a precision bandgap reference of typically 1.23v at pin pr. if programming the re- set threshold to other values than 4.7v is not re- quired this reference can be acessed. the imped- ance of pin pr is about 100k w . 7 conclusions the l4938 and l4938e family is a versatile low consumption voltage regulator family using state of the art technology and circuitry. as far as pos- sible it is designed to meet applicative require- ments respecting the posibility of using a low cost capacitors (with high esr values in the range of several ohms). the major design goal was providing the customer the best possible compromise between precision, low current con- sumption, dynamic response to distortions and electromagnetic compatibility. individual parame- ters of course can be beaten by devices opti- mised for one feature only sacrifying others (such as reference circuits that are optimised for preci- sion only, or in the other extreme standard topolo- gies with low precision optimised for dynamic be- haviour sacrifying for example current consumption requirements). to provide a good reference (1% at 25 deg. c, 2% throughout the whole temperature range) for precision analogue boards an enhanced bandgap reference circuit is implemented. samples evaluated show excep- tional low drift between 0 deg c and 125 deg. c. power on reset circuit features proper function downto vout1 = v be allowing applications with logic circuits starting to work with low supply volt- ages. the logic inputs en and si are hardened against negative input voltages. the whole circuit is hardened against emi as far as this is possible at the low quiescent current. application note 15/16
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications men- tioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without ex- press written approval of sgs-thomson microelectronics. ? 1994 sgs-thomson microelectronics - all rights reserved sgs-thomson microelectronics group of companies australia - brazil - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thaliand - united kingdom - u.s.a. application note 16/16

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